1. Field of the Invention
The present invention generally relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-229812, filed Oct. 12, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
The gate electrode of a memory cell selection transistor of a DRAM is integrally formed with a word line. A laminated structure of a polycrystalline silicon layer, a barrier metal layer, and a metal layer (hereinafter refer to as a polymetal structure) is known as a word line that includes the gate electrode. A laminated structure of a Ti layer, a TiN layer, and a W layer or the like (hereinafter referred to as a metal structure) are known as a bit line of a transistor. For example, Japanese Unexamined Patent Application, First Publication, No. JPA 2000-307084 discloses a memory cell including a word line having a poly-metal structure formed on a semiconductor substrate surface, a bit line having a metal structure formed over the word line, and a capacitor further formed over the bit line.
The third embodiment of Japanese Unexamined Patent Application, First Publication, No. JPA 2000-307084 discloses the constitution of a peripheral circuit that is a sense amplifier, wherein the gate electrode of a transistor of the peripheral circuit has one and the same polymetal structure as the word line of the memory cell, and is formed by the same process step.
Also, there is a description of a bit line of a memory having a metal structure extending up to the peripheral circuit, and connection being made to a gate electrode or a source/drain diffusion region of the peripheral circuit transistor via a contact plug.
In the configuration of Japanese Unexamined Patent Application, First Publication, No. JPA 2000-307084, because the bit line of the memory cell is formed at a position that is higher than the transistor of the peripheral circuit, a contact plug is necessary for the connection between the bit line and the transistor of the peripheral circuit.